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Intel moves beyond CMOS to MESO

January 14, 2022 2:20 PM Image Credit: Getty Images Did you miss a session from the Future of Work Summit? Head over to our Future of Work Summit on-demand library to stream. At the 2021 IEEE International Electron Devices Meeting (IEDM), Intel demonstrated for the first time a functional MESO (Magneto-Electric Spin-Orbit) transistor. MESO is what’s called…


Rainbow-colored image of various transistors laid out in a grid pattern.

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At the 2021 IEEE International Electron Devices Meeting (IEDM), Intel demonstrated for the first time a functional MESO (Magneto-Electric Spin-Orbit) transistor. MESO is also known as a “beyond CMOS” device. It is a revolutionary new method of building transistors (and computers) using room-temperature quantum materials. MESO could be 10 to 30 times more efficient than existing transistors and could help spur AI efforts across a variety of industries.

Although still in research, MESO represents the greatest advancement in computing since the introduction transistors. If it is commercialized, it would also lead to changes in electrical engineering courses. Intel’s previous theoretical research has shown that MESO could provide significant improvements over traditional transistors in terms of energy consumption and chip area. MESO could allow circuits to run at just 100mV, and would be especially promising for application in AI chips.

In the more recent demonstration, Intel showed the potential of the new transistor.

In 2021, Intel laid out its process roadmap through 2025, which it will also use to build its new Intel Foundry Service business. Most noteworthy from that roadmap is that, in 2024, Intel will make another big (but more evolutionary) change to the transistor with the introduction of RibbonFET and PowerVia.

Although MESO is still a futuristic technology, it’s important because it’s the only transistor (out of many that have been studied) that might be capable of replacing or augmenting conventional semiconductors. We will now dive into the science behind MESO.

How MESO goes beyond CMOS

Although computing existed long before the invention transistors (through devices like vacuum tubes), computing has only increased exponentially since then. Moore’s Law is a widely recognized trend that has seen these devices become ever smaller. They are able to scale well, but what makes them so popular is the on-off switch they offer circuit designers that provides a gain. Doping can also be used to control the properties of silicon, which is a semiconductor that is used in transistor fabrication. This means that conductivity can be controlled by doping silicon with impurities.

Over the years, particularly as the transistor entered nanoscale dimensions, there have been many improvements to speed up or reduce power consumption. One of the most significant improvements was the conversion of the transistor from a planar device into a 3D FinFET (wherein the fin extends beyond the original silicon wafer). This structure will be improved over the next few years by the gate-all transistor. It goes by many names, including the RibbonFET (Intel), or MCBFET(Samsung).

Despite these changes, the structure of a MOSFET remains fundamentally unchanged: current through the transistor channel is controlled by applying voltage to the gate. Because the gate is isolated from the conducting channel, current flows only from input to output. These contacts are called the source and drain.

Over time, many alternative structures were proposed. These structures are based on different physical properties and mechanisms, but they have the same on-off switch characteristics of a MOSFET.

The MOSFET can therefore be described as an electronic, charge-based device. Its working principle is electronic (electrostatic). Another device in the charge-based category is the tunnel FET. It uses the quantum mechanical property that tunneling has. Other types of devices include magneto-electronics and orbitronics.

Are these devices just curiosity for engineers and physicists to study or can they be used to replace silicon in high-volume production? This is due to the fundamental working principles that semiconductors have, which place a limit.

An on-off switch must have a significant current difference between the off- and on-states to work properly. This is done by applying voltage to the gate, as mentioned previously. The current through a transistor does not change arbitrarily when voltage is applied. The laws of thermodynamics and statistics limit the ability to produce current in semiconductors. Given the temperature at which electrons can move, there is a fundamental limit on how much current a transistor can absorb as voltage increases.

More specifically, the laws and principles of thermodynamics dictate a distribution of the energy available for electrons at a particular temperature (since temperature is merely their average energy). This distribution’s “tail” decays exponentially. When the transistor is switched off (reducing voltage below the threshold), the current will decrease exponentially with decreasing voltage. Importantly, this decay rate also depends on temperature.

This property is known as the subthreshold slope, and it’s expressed in terms of how many millivolts are required to increase or decrease the current by 10x. (The exact limit is ~60mV/dec, as it turns out.) This slope determines the operating voltage of a transistor. A transistor with a steeper slope will be able operate at a lower voltage. This would decrease its power consumption, and result in higher energy efficiency and speed. The slope is determined solely by thermodynamics. Therefore, it is impossible to increase the slope. This limitation is also known by the Boltzmann Tyranny.

Because the switching characteristics of a traditional CMOS device are limited by fundamental physics, it is possible to find devices that work on different physical mechanisms. This is why beyond-CMOS devices are so appealing.

A detailed graphic entitled Simulated switching energy and delay for 32-bit arithmetic logic unit circuit for CMOS and for various beyond-CMOS device options.

Although many alternatives have been suggested to the traditional transistor, decades of R&D have made silicon a formidable material. In a landmark research paper in 2017, Intel benchmarked about two dozen beyond-CMOS devices. The summary graph shows that not many devices are faster than HP CMOS and a few have lower power than LP CMOS. Overall, however, it didn’t appear that there was a single candidate that could be faster or use less power. It is unlikely that there are significant improvements to CMOS. However, it might be worth spending billions of dollars on R&D to create a switch suitable for high volume manufacturing. Other issues, such as cost, may also play a role.

Given the flexibility of CMOS, regular semiconductors, from low power to high-performance, analog to RF, high voltage to digital and so on, it is unlikely that CMOS technology ever will be completely replaced. Rather, a new technology would perhaps be integrated in combination with CMOS so that it could be used only for the circuits in a system where it delivers a real benefit.

A table showing the different computational variables and their examples based on class. Classes include charge, electric dipole, magnetic dipole, and orbital state.

How MESO goes beyond CMOS

More recently, a new kind of device (MESO) has emerged, invented by Intel and proposed in a 2018 paper. It is claimed that it could offer substantial advantages over CMOS. Since it would operate at just 100mV, it could result in 10 to 30 times higher efficiency. Intel claimed that it could increase logic density by five times. The MESO device is non-volatile, meaning it is saved when power is switched off, and also has spintronic capabilities, which could allow for new types of circuits that are suitable for AI.

“MESO is like a transistor – input voltage controls the current at the output (so it is electrical voltage in and current out like MOSFETs, but it switches at [approximately] 10x lower voltage than a MOSFET,” according to Intel. “Thus, wires only have top swing 10X lower voltage – this saves power.”

The architecture and physics for the MESO transistor are very different from traditional semiconductors. It makes extensive use of quantum effects, materials, and is similar to a transistor. MESO uses no less than three types of information carriers, according to the beyond-CMOS classification. These are electronics, magnetoelectronics and spintronics.

But the best thing about MESO is the fact that information is only transferred to the device via a standard charge-based interconnect and then out again as an electric current. The device converts the charge to magnetism by using the magnetoelectric effect and then to charge again using the spin-orbit effects. Below is an image of the device and information flow.

Detailed flowchart that shows how charge voltage changes through magnetoelectric effect to a charge to magnetism, how a spin-orbit effect changes it to magnetism to charge, and how a charge interconnect changes it again to a charge voltage as an output.

The device architecture is as follows. The input is a ferroelectric capacitance that is connected to an interconnect with regular charge-based charges. The magnetic properties of ferroelectric materials can be controlled by currents. This is how charge is converted into magnetism. Ferroelectric materials can also be used in an electric motor to convert current into magnetism. This ferroelectric material controls a nanomagnet, or ferromagnet that will point north or south depending upon its input.

Although this nanomagnet is the output state, it still needs to be converted to a current. This is done by a quantum effect known as a spin-orbit interaction or, more precisely, the inverse Rashba–Edelstein effect. A spin-orbit interaction is, in general, the interaction of an electron and a magnetic field. (Remember from quantum physics that every electron has an intrinsic magnetic moment called it its spin). It is a relativistic interaction between a particle’s motion and its spin within a potential. This is a more technical description. Rashba–Edelstein’s effect converts charge to spin. The inverse effect achieves the desired spin-to-charge conversion. The nanomagnet sends a current (Isupply) through it. Due to the inverse Rashba–Edelstein effect the output will either be positive or negative depending on which direction the nanomagnet is facing.

The switching property is achieved because the nanomagnet has an thresholding property. An input voltage controls it (through the ferroelectric materials), and this will point north or south. This will result in either positive or negative output current.

To make circuits using these devices, it is simply a matter connecting the output of one device with the input of another device. A positive current from the first device could charge the ferroelectric input capacitor in the second device. Conversely, a negative current would cause it to discharge. The thresholding property can be used to create “majority gate” using multiple voltages as input. A majority gate will produce a 1, if all its inputs are a 1. Intel claims a 5x increase in density. This is because it was already known from spintronics research that majority gate circuits could be smaller and require fewer transistors than traditional CMOS circuits.

In summary, the input charge converts to a magnetic signal through the ferroelectric materials, which control a nanomagnet. The output charge will be determined by this nanomagnet. It works through a quantum effect, which converts spin (induced by the nanomagnet into charge). It is analogous to an electric motor. The input current controls the motor. However, the motor is also used as an electrical generator to convert motion back into electricity, like a wind turbine.

The room temperature quantum materials, which Intel highlighted in 2018 as the main hurdles toward the physical realization of this device, are “correlated oxides” and “topological states of matter.”

In the larger context of beyond-CMOS electronics, traditional electronics are based upon spin/magnetism instead of charge. MESO solves the fundamental problem in the device’s readout due to the conversion back to charge at its output. From the 2018 paper: “The discovery of strong spin -charge coupling in topological matter via a Rashba-Edelstein or topological two-dimensional electron gas enables this proposal for a charge-driven, scalable logic computing device.” For comparison, in traditional spintronics, the spin for example decays exponentially through an interconnect.

In technical terms, the use spin for the transistor’s output is called a “collective status switch”. It is dependent on a collective order parameter that can have either plus or minus theta. This value can have two values which are basically just the spin being up/down. This switch is actually a switch because there are two outputs. However, the different mechanism it uses (based on the order parameter), overcomes the Boltzmann Tyranny that plagues traditional electronics.

Scatterplot that shows the relationship between power density and throughput for a variety of devices.

The graph above shows Intel’s benchmark results (based on simulation) from 2018 for a 32-bit ALU. MESO achieved a higher throughput density (TOPS/cm2) while using a lower power density than both the CMOS HP or LV.

Besides the lower operating voltage, Intel indicated that the different transistor architecture also allows for improvements in the interconnect, with resistance and capacitance requirements that are up to 100x “less stringent than conventional interconnects,” which in turn would reduce interconnect power by 10x. This might also contribute to MESO’s efficiency, since interconnects in modern chips could consume over 50% of the total power. Furthermore, Intel has demonstrated that the MESO device characteristics improve as the device is scaled further down (following a cubic trend), and MESO also promises integration and compatibility with CMOS.

Intel originally published a paper with various target specifications in order to achieve a 1aJ/bit device. Intel claims this is 30x lower than CMOS, which seems in the ballpark given that another source provides a lower limit of ~144aJ/bit in older 45nm process technology. Although 1aJ/bit was provided as the target, further in the paper estimates from 0.1 to 10 aJ/bit were also mentioned.

How these specifications could be translated into chip-scale specifications using circuits operating at possibly GHz-scale frequencies (if possible with MESO) remains to be seen. For comparison, state of the art commercial NPUs (neural processing units) achieve up to 10 TOPS/W at INT8 precision, which translates into 100 fJ/instruction or roughly 10 fJ/bit. This implies the circuit level is ~100x less efficient than a single inverter at its most efficient voltage-frequency operating point.

Applications in AI

In an interview with VentureBeat in 2019, Intel identified AI, in particular, as a promising application for the MESO device, rather than CPUs. There are a few reasons for this.

First of all, the MESO device’s low operating voltage may limit its ability to match the high frequencies of CMOS devices. MESO is more suitable for graphics and AI applications that require parallel operations, which run at lower speeds than a CPU.

Secondly, AI can take advantage of the various switching properties of MESO. Deep learning is particularly well-suited to the majority of MESO-compatible gates. By designing circuits that take advantage of majority gate, neural networks can be implemented with fewer transistors. “Majority Gates is the next door neighbor to a neuron. Deep neural networks are about weights and neurons. Intel stated that MESO technology, which can perform majority gates, is attractive to AI. Multiple inputs can be brought into the MESO magnet through a thresholding gate or’majority gate’. This is similar to the way neural networks use weights .”

to show the influence of nodes.

There could also be a more practical reason: “CPUs, which are the most commonplace when you’re building silicon, are oddly enough the hardest thing to build,” Amir Khosrowshahi, VP of Intel, said in the interview with VentureBeat. It’s a simpler architecture in AI. AI follows regular patterns. It mainly computes, interconnects, and stores memories. Neural networks can also tolerate inhomogeneities within the substrate. This technology is likely to be adopted in AI sooner than I expected. By 2025, it’s going to be the biggest thing.”

Timeline for MESO

As for the commercialization of MESO, the 2025 timeline might be ambitious given how many challenges are involved with bringing a fundamentally new technology into production. It has taken over a decade for improvements to standard transistors to be made into production.

Graphic that shows the incubation time for strained silicon (1992 to 2003), HKMG (1996 to 2007), Raised S/D (1993 to 2009), and MultiGates (1997 to 2011).

Based on the above discussion, there are two possible options. Either MESO could represent an alternative manufacturing technology that

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